1. Field of the Invention
This invention relates generally to delay systems and, more specifically, to a system and method that is able to switch between delay paths of differing magnitudes without creating any glitches or false edges.
2. Description of the Prior Art
Microcontrollers such as MICROCHIP TECHNOLOGY's PIC17C56 have a peripheral that is commonly referred to as a Synchronous Serial Port (SSP). The SSP is capable of supporting two serial communication protocols. The two protocols are the Serial Peripheral Interface (SPI) and the Inter-Integrated Circuit (I.sup.2 C). The SSP can only support one of these protocols at a time.
While incorporating a serial protocol on the SSP, it is necessary to select between two signals that are differing delayed versions of the same input signal. The I.sup.2 C protocol requires the selection to be made without creating any glitches or false edges during the transition between the differing delay paths. The I.sup.2 C protocol requires devices connected.to the bus to filter out any glitches of less than a certain amount (i.e., typically around 50 ns) on the input signals. For most SSP modules, the filtering of glitches is typically done by a circuit known as a pulse gobbler. The pulse gobbler uses weak devices and capacitors to delay the input signals for a period of time greater than the maximum glitch required to be filtered. Thus, if the input changes back to its initial state before it is allowed, the transition will be ignored. The filtering of the glitches is only required for the I.sup.2 C protocol. Since charging and discharging capacitors consume power, it is desirable to only have the pulse gobbler functioning when the SSP is operating in the I.sup.2 C mode.
The I.sup.2 C bus consists of two lines, a data line and a clock line. The 1.sup.2 C protocol defines that a transition on the data line while the clock line is high generates either a start bit or a stop bit. Thus, it is essential not to create any false edges on the data line when enabling and disabling the pulse gobbler.
Therefore a need existed to provide an improved system and method that is able to switch between delay paths of differing magnitudes. The improved system and method must be able to switch between delay paths of differing magnitudes without creating any glitches or false edges. This will allow a Synchronous Serial Port (SSP) operating under an Inter-Integrated Circuit (I.sup.2 C) protocol to switch between the differing delay versions of the same input signal without generating any glitches or false edges during the transition.